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NI AWR Design Environment 16.01R | 798.1 mb
Updated: Added NI AWR Design Environment 16.01 PDF Documentation
The software developer Cadence is pleased to announce the availability of AWR Design Environment 16.01. This platform provides RF/microwave engineers with integrated high-frequency circuit (Microwave Office), system (VSS), and EM (AXIEM/Analyst) simulation technologies and design automation to develop physically-realizable electronics ready for manufacturing.
AWR Design Environment V16.01 Release Notes
AWR Design Environment V16 What's New New in the AWR Design Environment
Improved Python Interface: AWR Design Environment API intelligent code completion. See Python.
Version Control Integration: Enables large group design projects by managing AWR Design Environment documents with version control software.
New in AWR Microwave Office
Dynamic Voiding, Smoothing, and Automatic Net Connectivity Extraction: New layout modes and tools that facilitate net management on large designs.
Robust Simplex Optimizers: Enhanced Simplex optimizers with variable step size.
Multi-Version Process Library (PDK) Support: Use multiple version of a PDK in the same project.
Job Scheduler Enhancements: Support for multiple remote queues and per EM document remote queues.
Parallel and Remote Circuit Simulation: Run long circuit simulation or optimization jobs in parallel, either locally or remotely.
Interoperability with Allegro and Virtuoso Platforms: Create and analyze RF/microwave IP in AWR Microwave Office and share schematic and layout with Virtuoso and Allegro platforms. This is a limited release feature.
Remote Linux EM Simulations: Run a remote Cadence AWR AXIEM 3D planar EM or Cadence AWR Analyst 3D FEM EM software simulation on a Linux LSF cluster.
AWR AXIEM Data Set Size Reduction: Exclude de-embedding network data from data sets.
Analyst Simulator Improvements: Various solver improvements.
Clarity 3D Solver Integration: Integration of the Cadence Clarity 3D Solver enables direct simulation of 3D EM structures from within the AWR Design Environment platform. This is a limited release feature.
Celsius Thermal Solver Integration: Run thermal analysis directly on structures created in the AWR Design Environment platform. This is a limited release feature.
New in VSS
Layout Trace Interconnect Modeling: Model linear interconnects in AWR VSS.
RF Amplifier Power Saturation Improvements: Improved modeling of RF amplifiers operating in saturation.
Frequency Multiplier Amplitude and Spur Level Improvements: Improved modeling of RF multipliers operating in saturation.
APSK Modulation: Support for generic and DVB-S2 and CCSDS communication standards.
New LDPC Encoding Schemes: Support for LDPC codes used in 5G NR (NSA and SA), DVB-S2, Wireless LAN, and other standards .
Version 16.01 Updates The Cadence AWR Design Environment platform version 16.01 software includes the following new features, enhancements, and user interface changes.
- Added Exists2 and Item2 API methods off of the CProcessLibraries collection. These methods both take library name and library version string parameters, so that a specific version can be selected.
- Added API access to the EM Port Material property and EMPort InfoText which provides access to the information on the Properties dialog box Info tab.
Cadence Unified Library
- Exporting the Cadence Unified Library due to port count mismatch between master and subcircuitschematic instances no longer causes a crash.
- The layout of a parameterized subcircuit using shape or layer modifiers is no longer exported without the correctly modified shapes.
- Ports are no longer dropped when exporting an EM structure to a Cadence Unified Library.
- The Export Cadence Unified Library dialog box Preset option selection is now retained after the dialog is re-opened.
- The Export Cadence Unified Library dialog box Tech Option is no longer reset when changing the Presets selection.
- When exporting the Cadence Unified Library for the first time from a project that uses a PDK with a tech attachment, the Export Cadence Unified Library dialog box Preset option is set to Board-Allegro by default. After the first export operation, your current selection is retained in the dialog box.
- The Cadence Unified Library Import Wizard now issues a warning when imported symbol pins do not fall on grid.
- The bottom boundary condition is now correctly exported to the Celsius solver when a material other than Air is defined with Er=1.
- Simulations using the Clarity solver now run if the project name includes "–" characters.
- Fixed a data set auto-delete issue which caused simulations to fail with the "Data set is missing or empty" DataSet_ReaderLock error.
- Importing DXF files with specified units now correctly detects specified units, but allows you to override with user-specified units.
- Various fixes are included to improve the stability of launching and running the Job Scheduler.
- Fixed an intermittent crash when using pipe IPC transport that could occur after a successful connection to a remote host.
- Improved job status messaging reliability between the user and scheduler nodes.
- Jobs are no longer erroneously scheduled on a compute node when the node is already in use.
- Improved responsiveness when canceling remote jobs, and fixed an issue which prevented cancellation of scheduled jobs.
- In the AWR Job Monitor dialog box, when Show Ended Jobs is notselected, the Job Monitor continuesto load additional jobs until there are either 50 "non-ended" jobs displayed, or all jobs have been loaded from the server.
- Multiple remote hosts can now be verified at the same time.
- Linux job queues version now reports as NA when verifying an LSF remote host.
- Improved error and status messages when Cadence AXIEM® 3D planar EM simulations on Linux fail to run.
- Improved theFetch Datasets operation. Data sets are pulled from the scheduler node, when possible, instead of pulling from the compute mode.
- The Circuit Options dialog box Nets/Voiding tab Show top level dynamic only option now only applies in voiding mode with "+" layer shapes that have a net name.
- Fixed an issue where pressing the Ctrl key to snap to gravity points(for example, vertex or midpoint) within an artwork cell placed in a circuit layout could miss the desired point in the cell due to grid settings.
- Improved schematic layout rendering of bondwire elements at various zoom levels.
Layout - EM
- Improved EM Clip Region layout processing to prevent exclusion ofsmallshapesfrom being copied to the EM layout.
- EM Clip Region processing of complex polygon shapes no longer causes missing shapes in the resulting EM layout.
- Adding a port to an Analyst software EM SUBCKT in an AXIEM structure no longer causes a crash.
- Re-extracting an EM structure while LVS, DRC, or thermal heat source markers are still displaced in the extracted
EM layout no longer causes a crash.
- Fixed an issue where removing a material definition in the Enclosure could cause boundary conditions to change.
- Fixed a material name conflict with hierarchical EM structures. The correct material properties are now applied when duplicate material names exist in a hierarchy.
- Eliminated the "Material not found in the EM Document" warning when unassigned materials are not in use.
- Export of an Analyst EM structure now generates the correct export files.
- EM ports no longer move to another edge when attached to a shape that is resized with a shape modifier.
- When a global definitions or schematic file is imported into a project, if the associated PDK is not loaded, a warning is now issued with an option to select another PDK when applicable.
- Copying elements between schematics that use different versions of a PDK now updates correctly.
- Switching to a newer version of a PDK during project open no longer causes a potential crash.
- Fixed a problem that could lead to a crash when a process library is added to an existing project and you click Yes in response to the question "Update the LPFand Global Definitions settings in schematics to match the process library?".
Measurements - Circuit
- Fixed a problem that could result in a crash when a measurement is converted to a Time Domain measurement that requires a voltage at a node where one is not available.
- Rectangular regions of a schematic are no longer hidden when an annotation is displayed on the schematic.
- Fixed a regression in V16.00 software that results in a crash when certain types of library elements are placed onto a schematic.
Simulation - Analyst
- Cadence Analyst 3D FEM EM extractions no longer result in the creation of duplicate EM subcircuit instances in the extracted hierarchical EM structure.
Simulation - APLAC
- The NLCAPA element no longer causes a harmonic balance convergence problem.
- Long lines displayed in a Cadence APLAC® HP simulator data set Solver Information dialog box Simulation Log tab are now broken into multiple lines to prevent an "Error reading data set" error.
- X-parameter model phase is no longer erroneous when the mixing product frequency is negative.
Simulation - Linear
- Fixed a problem that resulted in an error message, "Storage allocation error, number of ports does not match matrix size", when trying to simulate a schematic containing a PORT_NAME element with a bus or bundle specification.
Simulation - RF Budget
- When AMP_F is configured to generate DCPOUT and the data file/IMPLTYP settings result in an AM/AM-AM/PM model being used, the DCPOUT value is fixed so it is no longer always 0 for RF Budget Analysis and RF Inspector simulations.
Simulation - Systems
- Fixed a crash that could occur when starting a system simulation on a document with PORT_SRC elements after removing a process library from a project or changing a library version.
Tuning, Yield Analysis and Optimization
- Undoing a manual entry in the Value column of the Tuner dialog box no longer causes a crash
- Further filtering of a property grid once a Boolean column is filtered now functions correctly.
- Using Redo after Undo in a property grid now restores the Upper column value when the Lower and Upper limits are set using "%" or "#" in the Value column.
Wizards - PCB Import
- An error message is now issued indicating why the drill file could not be imported if the PCB Import wizard crashes when there is no tooling information in a drill file header.
Wizards - Stability Analysis using STAN
- Stability Analysis using STAN Wizard now issues a warning if poles/zeros are found in the same point. A secondary parameter is added to enable automatic phase tolerance scaling.
× NI AWR Design Environment 16.01R Close
× NI AWR Design Environment 16.01R Close
The Cadence AWR Design Environment platform electronic design automation (EDA) software suite provides RF/microwave engineers with access to innovative high-frequency circuit, system, and electromagnetic (EM) analysis technologies. Today’s microwave and RF engineers use this powerful, open platform to design wireless products ranging from base stations to cellphones to satellite communications. The AWR Design Environment software advantages are straightforward: an intuitive use model that delivers an exceptional user experience (UX), robust simulation technologies that deliver both speed and accuracy, and an open design flow supporting data to/from third-party tools.
AWR Design Environment
Cadence Design Systems, Inc. announced that it has completed the acquisition of AWR Corporation from National Instruments Corporation. The addition of AWR’s technologies and talent will further expand Cadence’s reach into 5G RF communications and support system innovation for the aerospace and defense, automotive and wireless market segments.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Product: NI AWR Design Environment
Version: 16.01R Build 12506 Rev2 (130759) with PDF Documentation
Supported Architectures: x64
Website Home Page : www.awr.com
Languages Supported: english
System Requirements: PC *
Size: 798.1 mb
* System Requirements: × NI AWR Design Environment 16.01R Close
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