× Cadence INCISIVE version 15.20.001 Close
Cadence INCISIVE version 15.20.001 | 9.3 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled INCISIVE 15.20.001, the single-kernel verification platform for nanometer-scale designs that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains.
Defects fixed in INCISIVE 15.20.001 1489447 DBG_ANALYZER idaDefineStyle() internal assertion when the same style is defined twice
1489431 DBG_ANALYZER idaDefineStyle() has character restrictions in style name which do not trigger an error
1503435 DBG_ANALYZER Problem in sending e events to waves with IDA
1469726 DBG_ANALYZER copy command error when using ida_database -open -name /tmp/aaa/ida.db command
1447284 DBG_ANALYZER IDA shows wrong stack when using "first of"
1471913 DBG_ANALYZER No syntax highlighting for file with .vh extension (file meant to be `included)
1342814 DBG_ANALYZER ESW_BETA: View of waveform window follow the DEBUG_LOCATION Marker.
1456402 DBG_ANALYZER Missing disassembly
1437729 DBG_ANALYZER Breaking in assembly window
1514089 DBG_ANALYZER [ESWD] Multi-image PC trace mode - No disassembly, No second assembler source
1510976 DBG_ANALYZER [ESWD] PC trace mode warning pop-up every time debug cores changed
1353636 DBG_ANALYZER ESW_BETA : breakpoints not saved when saving user state
1421826 DBG_ANALYZER Stars manager for ESWD shows name "EMPTY DATA" for all items
1493237 DBG_ANALYZER "Cores" window refresh issue
1501065 DBG_ANALYZER [ESWD] Callstack window doesn't work properly (showing redundant functions)
1507098 DBG_ANALYZER not able to use the "go to previous operation" of a core
1487186 DBG_ANALYZER Disassembly is not stepping into statically linked library function
1507107 DBG_ANALYZER multi-core issue in disassembly / source / WF
1409224 DBG_ANALYZER better granularity for PC / ASM code link
1469010 DBG_ANALYZER OS signal 11 when restoring User State
1500510 DBG_ANALYZER [ESWD] supporting step/back into dis-assembly window
1539761 DBG_ANALYZER missing disassembly with multi-elf processor trace mode
1510161 DBG_ANALYZER assignment via set_value() is not recorded using debug analyzer
1504289 DBG_ANALYZER output from filtered method is shown as emty (NULL structs and empty lists).
1338868 DBG_ANALYZER debug_analyzer script gives error message with garbage when using -file with the irun command
1498853 DBG_ANALYZER IDA: OPTNOML: Multiple -R option specified, only 1 required.
1378379 DBG_ANALYZER ida feature request - db filename in title bar of smartlog
1463108 DBG_ANALYZER Save user state dialogue box defaults to .sav
1483023 DBG_ANALYZER Monospace fond for disassembly code
1287626 DBG_ANALYZER when restoring the 'value' attribute after it was removed - the radix option disappears from the drop-down menu
1345405 DBG_ANALYZER debug analyzer gui does not comes up
1487960 DBG_ANALYZER Undocked source debugger window is fixed on top
1491320 DBG_ANALYZER issue when changing variableS radix
1501039 DBG_ANALYZER [ESWD] cannot change dis-assembly window to monospace font
1492718 DBG_ANALYZER Cannot change radix anymore after removing columns in time tables
1501053 DBG_ANALYZER [ESWD] Changing Radix on the Variables doesn't work
1501055 DBG_ANALYZER [ESWD] set monospace font as default of Source window
1497620 DBG_ANALYZER filtering issues of variables
1501018 DBG_ANALYZER [ESWD] Support showing Japanese charactoers on the Source Viewer
1493952 DBG_ANALYZER GUI freeze when changing Time table radix
1400055 DBG_ANALYZER Order tools are set in the Path impacts simulator behavior.
1395880 DBG_ANALYZER Unconsitent color map case sensitivity
1512865 DBG_ANALYZER 'Jump Address' of Indago ESWD memory viewer doesn't work on testcase
1512591 DBG_ANALYZER 'Lowest Address' and 'Highest Address' forms of the memory viewer tab are not wide enough
1153467 DBG_ANALYZER Support refinement for temporal evaluations
1436515 DBG_ANALYZER When recording from a particular time, ida does not record to smartlog.
1449022 DBG_ANALYZER Recording of $fwrite results in huge log
1451972 DBG_ANALYZER nested deep_copy not recorded
1438118 DBG_ANALYZER messages that contain *E that are not error messages are starred when i invoke the GUI (marked as error message
1438652 DBG_ANALYZER direct access arrow is shown on a specific line , but the blue scope indication is missing.
1470953 DBG_ANALYZER IDA - Warning/Error should be given when nothing is matching in the ignore_sv_files argument
1457251 DBG_ANALYZER Recording Issue: Flow information not recorded
1481643 DBG_ANALYZER IDA performance: -sv_flow option 40 times slower than without IDA
1460415 DBG_ANALYZER Performance: 10X Slowdown when running with both -log and -wave
1463116 DBG_ANALYZER Bad formatting of sprintf messages in smartlog
1366672 DBG_ANALYZER searcher doesn't show progress status
1438131 DBG_ANALYZER Add Smart print to log window focus
1519825 DBG_ANALYZER Support having direct access arrows from the smartLog when using VMM
1420981 DBG_ANALYZER Not able to filter message by destination file
1463083 DBG_ANALYZER Smartlog query not saving end time properly
1507549 DBG_ANALYZER Value of packed union is not displayed in the Variables window of IDA
1342452 DBG_ANALYZER IDA can not open arrays which are located under a struct in SV, as opposed to a class
1465236 DBG_ANALYZER wrong value shown in the variables table for automatic variable
1524190 DBG_ANALYZER variable table shows incorrect value while LOG shows correct value of local variable
1487925 DBG_ANALYZER watch window shows N/A values for local variables and function params in 14.20.017-s. this works fine in previous vers
1506540 DBG_ANALYZER OS Signal11 when clicking class in variable window
1343169 DBG_ANALYZER virtual interface values are not shown in the variables table when the vif is inside a class
1533887 DBG_ANALYZER bug in recording of a value of a function output
1379669 DBG_ANALYZER Be able to add array elements to time tables
1379670 DBG_ANALYZER Be able to see more levels of hierarchy in time tables
1494228 DBG_ESW [ESWD] Encountered a parse error with R4 and M3
1487538 DBG_ESW Add an API to specify an offset of the recorded TARMAC
1490182 DBG_ESW ESWD crash when generating DB
1475649 DBG_ESW Need descriptive error message for mismatched arch kind and tarmac file when creating esw db
1517040 DBG_ESW [ESWD] Internal error when giving arch config file in pcshm flow
1507470 DBG_ESW need a way to change disassembly_tool for ARM cores
1486439 DBG_ESW Unclear error from Indago ESWD on architecture configuration file for generic processor trace format with single mode
1540477 DBG_ESW ESWD not showing global variables
1495036 DBG_ESW ESWD config disassembly_tool options issue
1469829 DBG_ESW Regression failure fixes on avs151/tip_in
1514115 DBG_ESW [ESWD] PC = FFFFFFFF in 32-bit mode
1512684 DBG_ESW [ESWD] PC-trace mode 64-bit PC truncated into 32-bit in eswtrace.shm
1510510 DBG_ESW Cannot trace a specific ESW function invocation, while the doc says it can
1501517 DBG_ESW [ESWD] multiple warn/error of probe variable causes internal exception
1504407 DBG_ESW [ESWD] [SOIO] Register probes installed using short name are not recorded under correct heirarchy in SHM
1501046 DBG_ESW [ESWD] esw -probe -variable produces no output for pointer types int *, long * etc
1440172 DBG_ESW Call stack shows "unknown function" from assembly source code
1440166 DBG_ESW "Step over" & "run to method start/end" funtion from assembly source code does not work
1442127 DBG_ESW Executed source lines are not shown as executed in source browser
1437556 DBG_ESW Step over function does not work
1494534 DBG_ESW Unclear error from Indago ESWD for user configuration file
1492677 DBG_ESW case issue for db creation
1492686 DBG_ESW multi-elf issue in processor trace mode
1507104 DBG_ESW Indago GUI lost due to ESWD tool failure when getting call stack frames
1506922 DBG_ESW not able to start indago
1507618 DBG_ESW ESWD tool failure for DWARF functions with 0 address ranges
1465406 DBG_ESW Internal Exception error when accessing global variables
1492959 DBG_ESW Does register probe capture over 0x8000000 value?
1491718 DBG_ESW [ESWD] probing register cause internal exception
1308369 DBG_SIMCOMPARE SimCompare prematurely displays success though comparison is still running
1441133 DBG_SIMVISION SimVision incorrectly uses vpi_handle(vpiConstraintExpr, …) rather than vpi_iterate(vpiConstraintExpr, …)
1441554 DBG_SIMVISION Enable Simvision to query for rand_mode not only in randomization call
1452811 DBG_SIMVISION Users must be able to see rand_mode within the watch window at any time, not just within randomize calls
1501192 DBG_SIMVISION simvision fit data y-axis does not work
1479075 DBG_SIMVISION IDA seems to become unresponsive.
1442918 DBG_SIMVISION Simvision shows internal errors while retrieving class objects
1278334 DBG_SIMVISION checkbutton to filter LP objects in the Signal pane of the Design Browser
1496926 DBG_SIMVISION Is there a reason why uvm_subscriber aren't showing up in UVM-hier in Design browser?
1513058 DBG_SIMVISION IES becomes unresponsive when probing uvm hier.
1456773 DBG_SIMVISION "-nclibdirname" option in simvision dosn't work.
1511971 DBG_SIMVISION Unable to do Design File Search with 14.21.046 in customer's environment
1507518 DBG_SIMVISION SimVision Issue: Reinvoke vs Exit Setting
1464187 DBG_SIMVISION multiple progressdialog processes running
1453888 DBG_SIMVISION Simvision bring-up time is slower w/ 1801
1450558 DBG_SIMVISION simvision performance is poor when sim includes UPF
1493528 DBG_SIMVISION Database restore doesn't work for power domain information
1463938 DBG_SIMVISION simulation becomes unresposive when simvison is started with command script, but no probe command
1447303 DBG_SIMVISION missing connection in schematic tracer
1438144 DBG_SIMVISION Verilog processes are not sent to the waveform window from the schematic.
1446859 DBG_SIMVISION Sending certain VHDL record element to Schematic Window causes fatal error in ncsim
1354392 DBG_SIMVISION Please make showing the RTL symbols in the schematic viewer on by default
1477986 DBG_SIMVISION Simvision issues with Light weight debug snapshot fetaure
1449236 DBG_SIMVISION Trace drivers takes 10 minutes
1519170 DBG_SIMVISION driver tracing reports an expression as contributor but cannot trace further
1367405 DBG_SIMVISION Source browser does not work correctly for signal/instance which has Extended Identifier.
1378630 DBG_SIMVISION Moving in stack in Simvision takes a very long time
1453233 DBG_SIMVISION Source browser - design source files - filtering usability issues
1517338 DBG_SIMVISION Applying filters from the history does not work for "Design Files" tab of Source Browser
1433280 DBG_SIMVISION using $uvm:{} syntax for probing doesn't show source code in post processing
1446473 DBG_SIMVISION FSM viewer issue of VHDL design
0971655 DBG_SIMVISION Enhancement request: Turn off cursor movement while tracing.
1124885 DBG_SIMVISION Simvision timestamp (cursor) moves when double clicked in simvision
1118560 DBG_SIMVISION How to trace driver in the Source Browser without having the time marker change position
1338709 DBG_SIMVISION Simvision timestamp (cursor) moves when double clicked in simvision
1370797 DBG_SIMVISION SimVision to add an option that allows structs to display their first field in the waveform display
1457032 DBG_SIMVISION empty group does mess .svcf creation with missing trailing curly brace
1515576 DBG_SIMVISION Svwf is not loading in simvision
1370791 DBG_SIMVISION SimVision to add an option that allows Verilog fixed length strings to be automatically recognized as ASCII
1419402 DBG_SIMVISION trace driver in the Source Browser without changing the time cursor position
1525665 DBG_SIMVISION Simvision signal script saved incorrectly with empty groups
1410051 DBG_SIMVISION Unable to select signals using CTRL-A from signal selector area in wave window.
1498055 DBG_SIMVISION Default displayed radix of bit [31:0] in Source Browser should be hex
1485393 DBG_SIMVISION Assertion contributors are dublicated in waveform
1268474 DBG_TANGO IDA busy signal doesn't light up when expanding elements of the hierarchy
1530074 FUNC_SAFETY Large fault set gets the elaboration hang
1519974 FUNC_SAFETY … in fault_target does give a fatal error during elaboration
1528896 FUNC_SAFETY The elaboration with IFSS becomes unresponsive with netlist
1494397 FUNC_SAFETY elaboration run forever if fault instrumentation is enabled
1535955 FUNC_SAFETY NCELAB tool failure with gatelevel ifss simulation
1531051 FUNC_SAFETY Internal Exception when targeting SEU only during elaboration
1530021 FUNC_SAFETY IFR fails when snapshot does not have fault information
1534518 FUNC_SAFETY OS 11 on elaboration
1439522 FUNC_SAFETY glitches on good run simulation that are not on standard simulation
1501354 FUNC_SAFETY IFSS ncsim tool failure when using snapshot chekpoints and also having any dummy SystemC TB module being used.
1535651 FUNC_SAFETY Fault simulation memory usage increases after reset and rerun
1332522 HAL "When others => null" state give warning [EMPSTM] even if all the state of cases are covered
1459730 HAL halcheck: *E,NULLRG & halsynth: *E,EMTFNC comparing results with RC
1289791 HAL halcheck: *F,HALSIG unable to proceed further due to a critical error
1413303 HAL Support for NULLRG, NULSLC and NULLSTR halsynth error
1416154 HAL HALSIG
1424631 HAL Nodes fed into the flop reported as INF in HAL test coverage report
1416210 HAL halcheck: *F,HALSIG: Unable to proceed further due to a critical error.
1414033 HAL HAL "designinfo" broken when checked into design repository
1503424 HAL hal stops with BLDSTP using -halsynth_nxg but not without
1465979 HAL halsynth: *W,BBXSIG message – how to increase the limit
1360783 HAL HAL - SLVUSE Violations - support for VHDL record types
1353155 HAL Upgrade NEGIDX warning to error
1418392 HAL HAL Enhacement: Accumulation of filters
1249266 HAL HAL Rule IPRTEX and EXPIPC: need dummy tie off that isn't flagged by rule, ie ONE_TIE, ZERO_TIE
1313872 HAL unexpected hal message SLVUSE with VHDL record type.
1551500 HAL halcheck: *W,SLVUSE: Variable 'dacdatabsel' appearing in the sensitivity list is not used in the process block.
1375842 HAL HAL warning SYNTXZ issued when OTHERS path does not exist
1447174 HAL Linting enhancement: Support for SystemVerilog Case-Inside
1451648 HAL halsynth: *F,CFESIG expExpr* getParamValueforUnpackedData(ss
1426472 HAL halsynth: *E,SYSIGN : SystemVerilog 'case inside' construct is not supported
1521001 IEV Error in supporting the local variable in property and sequence in IEV.
1285285 IEV IFV DRM random crash on LSF
1293053 IEV Tool failure in IEV using Reset Flow
1287618 IEV illegal termination on formalverifier
1424713 IEV REPERR at formalbuild step, not able to generate coverage, Tool run time becomes huge
1517459 IEV Parallel persistent setting causing problem with Broadcom UNR
1504943 IEV IEV tool failure during formalbuild
1500824 IEV formal build INTERNAL EXCEPTION: xst_hasprotected on invalid VST type
1530986 IEV IEV 14.20.013 UNR parallel_persistent_mode is no working
1410944 IEV UNR execution with Primary and incremental sanpshot environment
1445093 IFV IFV Connectivity : Assertions not generated on 14.20, while they are being properly generated on version 13.10.020
1418297 IFV bb_gen problems with alias_module and tran switch
1261618 IFV IFV SGE Distribution issue
1253454 IFV Tool failure with IFV in LSF mode
1412694 IFV IFV tool failure at formalbuild step
1481086 IFV CFESIG in nc_mirror call when running formalbuild
1301822 IFV IEV 14.1 Errors Out when Exiting the Tool in GUI Mode
1039280 IUS_AMSD compcnfg lib binding does not work with BIND2
1030288 IUS_AMSD compcnfg setting not working in BIND2 flow
1374421 IUS_AMSD Enhance reffile to use ENV variables in its path
1508300 IUS_AMSD ncelab: *F,INTERR: INTERNAL EXCEPTION
1527469 IUS_AMSD AMS could not handle "pwr" function in SPICE model
1509679 IUS_AMSD irun INTERR during parsing when module w/ `uselib is included twice w/ -amscompilefile
1520464 IUS_AMSD amsspice segmentation fault with error code 6
1514216 IUS_AMSD makelib compilation flow always requires a dummy file to be always present outside
1533291 IUS_AMSD Elab failure with cosim in spectre
1416409 IUS_AMSD support systemVerilog bind statements in AMS runs - when the bind statements are on SPICE blocks
1504070 IUS_AMSD elab tool failure in ius14.2s17 and beyond (works in ius14.1s11)
1490276 IUS_AMSD Files created by irun do not honor umask setting
1495950 IUS_AMSD VCD bus input don't reach digital blocks in AMS
1500210 IUS_AMSD irun versions after 14.20 do not show symbolic link but just fully resolved path
1506405 IUS_AMSD amsd control file no longer works for spice in EXT HDL in ADE L
0815071 IUS_AMSD Ncelab fails for SV assertions on Spice nets
1039278 IUS_AMSD Compcnfg view binding does not work with BIND2
1032729 IUS_AMSD Compcnfg option for view binding is not working
1302734 IUS_AMSD Add support fo rrelative paths and shell variable paths to amsd portmap reffile.
1181446 IUS_AMSD Allow reffile value to be specified via a UNIX env var
1306648 IUS_AMSD How to handle a cellview with multiple .v/.vams views in UNL?
1472884 IUS_AMSD Internal error in UNL testcase when switching to 15.10
1461085 IUS_AMSD UNL is erroring out on a cell totally unrelated to the actual problem in the design - fix elaboration error message
1508174 IUS_AMSD Incorrect current value reported by $cgav function
1517358 IUS_AMSD Incisive 14.2 and 15.1 doesn't queue for MMSIM tokens
1510624 IUS_AMSD AMS license queueing broken in INCISIVE 14.2 and 15.1
1434906 IUS_AMSD AMSD IEEE1801 enhanced test case for DoT flow
1420988 IUS_AMSD AMSD IEEE1801 Parametrizable power supply connect modules
1455231 IUS_AMSD AMS with CPF fails during elaboration
1445241 IUS_AMSD wreal simulations stops due to INPVINT/NINDEX0 errors
1458176 IUS_AMSD AMSD IEEE1801 Elaboration error LPACVF in case cds_implicit_tmpdir is used or when using ASSIGN TMP attribute
1515404 IUS_AMSD Incorrect conversion of UPF value when using the default predefined UPF_GNDZERO2SV_LOGIC table in UPF sims
1512698 IUS_AMSD the L2R_LPS on wreal array cause ncsim tool failure
1442652 IUS_AMSD AMSD IEEE1801 ncsim internal error with EAP build and extended ams test case
1425093 IUS_AMSD Remove VPI limitations in power smart IEs
1421003 IUS_AMSD AMSD IEEE1801 Include power supply connect modules in the IE CE report files generated by irun
1435059 IUS_AMSD cu_connected_through_port: the sizes for child and parent don't match (psize(10)
1461537 IUS_AMSD too many warnings during AMSLP simulations
1475348 IUS_AMSD ncelab becomes unresponsive on mixed-signal design with wreal models and CPF
1472406 IUS_AMSD The AMSLPS VPI function encountered an error
1522794 IUS_AMSD Omitting file name argument to +amsinfofile results in fatal error
1488134 IUS_AMSD ncelab tool failure when real variable connect to electrical port
1374189 IUS_AMSD SV interconnect array connected to different nettype fails
1374201 IUS_AMSD add the support of wreal of MSIE
1452767 IUS_AMSD Need incremental elab for design containing AMS
1524515 IUS_AMSD default discipline does not work on inh-conn
1434628 IUS_AMSD ncelab: *F,INTERR: INTERNAL EXCEPTION
1435130 IUS_AMSD ncelab fails to elaborate with inherited connections connect rules
1487543 IUS_AMSD ncelab internal error for chkdigdisp
1493313 IUS_AMSD NCSIM causes a tool failure on request for value from SimVision
1486025 IUS_AMSD ncelab Internal Exception when LP/CPF is used with SV and DMS
1490907 IUS_AMSD ncelab gives internal exception error with "ams_add_to_td_list - parent data already in child" message
1491243 IUS_AMSD ncelab tool failure because of ie card specification
0820779 IUS_AMSD enable wrealXState in VHDL for Mixed language Simulation
1461656 IUS_AMSD design gets Internal Error during ncelab 15.1 with amssie defaulted on
1472413 IUS_AMSD ncelab sv_seghandler - trapno -1 addr(0x20000024)
1491014 IUS_AMSD Adding a few irrelevant lines to an LP/DMS example prevents tool failure
1481792 IUS_AMSD Testcase fails with ihnConn_findSB - unresolved OOMR
1461308 IUS_AMSD ncelab Internal Exception with incisive version 14.20.009
1476233 IUS_AMSD NCELAB internal exception when using amsoptie
1482368 IUS_AMSD INTERNAL EXCEPTION in ncelab 15.10-s002
1469542 IUS_AMSD SV with nettypes and VHDL - crash
1371258 IUS_AMSD driver_update in conditional statement causes internal error
1345933 IUS_AMSD cannot issue an ida_probe command when the analog solver is present.
1498945 IUS_AMSD Simulation with warning WRMNZD when real has multiple drivers.
1529870 IUS_AMSD irun becomes unresponsive on compilation
1291730 IUS_AMSD $resolved_wudn_name needs further enhancement to give the top most (highest hierarchical level) name - always
1411610 IUS_AMSD E,NOTSUP occurs for task or function used in sv module
1483802 IUS_AMSD ncvlog internal error while initializing integer array in verilogams module
1488065 IUS_AMSD ncsim internal exception using -use_cm switch
1453271 IUS_AMSD Redundant WRMNZD warning for wreal
1521277 IUS_AMSD tran gate working incorrectly in wreal (DMS) simulations
1484356 IUS_AMSD irun ignores ie card in SV-UVM-AMSD flow when -run_coerce is on. Breaks multi-supply AMS verifications.
1501128 IUS_AMSD Modulus of a wreal produces an internal error
1448940 IUS_ASSERTION Question regarding "-nosort" for TCL assertion commands
1494031 IUS_ASSERTION Tool failure with -assertdebug
1494633 IUS_ASSERTION ncsim exits for MAX_ERROR when simvision causes UVMNCP error after an assertion
1484227 IUS_ASSERTION -assert_logging_error_off causes an RPTNAG error in 15.10.002 and newer
1413840 IUS_ASSERTION IUS14.2s004 fails by giving an assertion error during simulation
1482904 IUS_ASSERTION Simvision design search causes simulator Internal Exception
1465553 IUS_ASSERTION "-assert_logging_error_off" not changing the exit status to 0 for ncsim on assertion failure in 1420
1479353 IUS_ASSERTION IUS doesn't display ASRTST error after ncsc_assertion_on().
1467473 IUS_CORE_CODEGEN ncvlog_cg: *F,INTERR: INTERNAL EXCEPTION
1431843 IUS_CORE_CODEGEN long elaboration time with ncvlog_cg
1368266 IUS_CORE_CODEGEN always_comb hangs at time 0 with -linedebug or -access options.
1453429 IUS_CORE_CODEGEN ncsim becomes unresponsive in multiple always @* that references different bits of a signal
1437028 IUS_CORE_CODEGEN IUS simulation becomes unresonsive at 0ns.
1446109 IUS_CORE_CODEGEN internal exception when compiling UVM scoreboard : ncvlog_cg : gq_setwait - null/!SVHR VXLF_HEAP cached t_t
1457281 IUS_CORE_CODEGEN Ncvlog_cg failure in 14.22.012
1284933 IUS_CORE_CODEGEN ncsim goes into infinite loop by always@* in generate-for block
1505164 IUS_CORE_CODEGEN ncvlog_cg : Internal Exception Error while running a testcase
1292914 IUS_CORE_CODEGEN ability to handle longest static prefix of net array for always_comb/always_latch
1490722 IUS_CORE_CODEGEN Compilation Internal Exception 14.20.012 ( but works well with 12.20.30)
1503030 IUS_CORE_CODEGEN ncvlog_cg crashes with 15.10.00x
1504550 IUS_CORE_CODEGEN gc_addrelocation - offset out of bounds
1094848 IUS_CORE_CODEGEN *W,NLSPNA: longest static prefix for always_comb/always_latch is not supported for net array/struct
1238063 IUS_CORE_CODEGEN Warning NLSPNA longest static prefix for always_comb/always_latch
1313322 IUS_CORE_CODEGEN NLSPNA warning repeated for the same array
1405890 IUS_CORE_CODEGEN ncvlog_cg fatal error while executing tb generated from ET
1415019 IUS_CORE_CODEGEN ncvlog crash gc_addrelocation - offset field too large (2147483731d instructions)
1401907 IUS_CORE_CODEGEN Ncvlog crash gc_addrelocation - offset field too large (2147483731d instructions) after using -sparsearray switch
1474312 IUS_CORE_CODEGEN INTERNAL EXCEPTION: ncvlog_cg: gq_slfix - next sload not followed by a move
1462348 IUS_CORE_CODEGEN Ncvlog_cg fails in 14.20.014
1467329 IUS_CORE_CODEGEN ncvlog_cg: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Unexpected signal #11
1474413 IUS_CORE_CODEGEN ncelab: *F,CGFAIL: Code generation failed for one or more modules.
1481743 IUS_CORE_CODEGEN testcase generates " gq_auto_swbwo - not found" crash
1468610 IUS_CORE_CODEGEN ncvlog_cg(64): Unexpected signal #11, program terminated (null)
1473363 IUS_CORE_CODEGEN [Mini regression] AVSFST14.22.014,015,016 Performance degradation with ATPG Parallel case
1470934 IUS_CORE_CODEGEN Customer got 'gc_addrelocation - offset field too large (2147483669d instructions)' crash
1471986 IUS_CORE_CODEGEN Running into internal gq_bopadd -d not tmp during code generation with 14.22.016
1535439 IUS_CORE_CODEGEN ncvlog_cg Internal Exception with internal error with code "gq_lhsvs - variable LHS ZDC"
1452629 IUS_CORE_ELAB INTERNAL EXCEPTION when elaboration using -nncbind flag on iBeta IUS15.10_v008
1443676 IUS_CORE_ELAB Request to invoke warning message when the flag 'ay' is used without 'alibext' flag
1453648 IUS_CORE_ELAB MSIE ncelab crash : tim_is_tch_dead - failed to find the provided tcheck
1443303 IUS_CORE_ELAB Compile error during parse spawned by elaboration bind
1496167 IUS_CORE_ELAB F,INTERR :gen_vst_expr - illegal KIND of expression
1485191 IUS_CORE_ELAB signal value does not propagate correctly to instance port.
1502374 IUS_CORE_ELAB ssue to bind a SV module on 2 snapshots using ncelab option -extbind
1500407 IUS_CORE_ELAB "irun -binding" does not work . However "ncelab -binding" works for 3-step flow.
1399477 IUS_CORE_ELAB ncvlog_cg fails on the attached testcase
1519096 IUS_CORE_ELAB NOTPAR msg seen when including lps_1801 during elab
1525865 IUS_CORE_ELAB INTERNAL EXCEPTION when using ER for 1524762
1512985 IUS_CORE_ELAB ncelab: *E,NOTPAR (./dut.sv,24 69): Illegal operand for constant expression [4(IEEE)].
1433004 IUS_CORE_ELAB part of vector slice is out of range and incisive returns the whole slice as 0
0786533 IUS_CORE_ELAB Implement a bbox flow to optimize IP reuse
1282432 IUS_CORE_ELAB ncelab CUMXVP Unsupported variable input port at mixed language boundary : VHDL array and unpacked array of typedef
1335152 IUS_CORE_ELAB [VHDL/SV] [Package Import] ncelab: *ECUMXVP Unsupported variable input port at mixed language boundary
1323887 IUS_CORE_ELAB Enhancment request to pass vhdl real to systemverilog
1338061 IUS_CORE_ELAB How to pass data between VHDL (record) and SystemVerilog (struct). TC attached, please review
1455243 IUS_CORE_ELAB array type imported with bounds defined by function gives cu_add_driver_to_vhdl_net_driver_list - net is boundary_net
1455096 IUS_CORE_ELAB Invalid assertion failure comparing sv bind port to vhdl signal via sv oomr with package import
1455233 IUS_CORE_ELAB array type imported with bounds defined by function call used in SVA gives "ast_integer_literal() - bad class"
1448712 IUS_CORE_ELAB Failure binding sv module to vhdl using ports defined via package import: MESSAGE: sv_seghandler - trapno -1 addr(0x3)
1448689 IUS_CORE_ELAB VHDL Package Import: Unable to connect SV enum port to VHDL enum using type imported from VHDL package
1455182 IUS_CORE_ELAB ncelab *E,TYCMPAT comparing sv port defined via vhdl package import to signal of same type in vhdl via OOMR
1447963 IUS_CORE_ELAB ncelab Internal Exception with nettmp_fetch - id out of range when binding SVA to VHDL
0881933 IUS_CORE_ELAB MAINVR - Support for mapping of verilog var unpacked array port to VHDL port
1476711 IUS_CORE_ELAB Mixed SV->VHDL OOMR Internal MESSAGE: gq_e_relational - RAWDATA/QP_CLASS
1485313 IUS_CORE_ELAB VHDL/SV ncelab INTERNAL ERROR: Unexpected data type mapping - finalize_sys_vlog_to_vhdl_data_type
1319766 IUS_CORE_ELAB Support connecting SV struct ports to VHDL record type ports through SV bind construct
1316040 IUS_CORE_ELAB SV with input port of certain types receive MAINVR error during ncelab when instantiated in VHDL
1476725 IUS_CORE_ELAB Mixed SV->VHDL Internal MESSAGE: dto_array_left - not array
1477032 IUS_CORE_ELAB ncelab INTERR: nettmp_fetch - id 34230294 is out of range
1506857 IUS_CORE_ELAB NC Internal Exception during elaboration
1445771 IUS_CORE_ELAB C compile failing during MSIE incremental elab
1436273 IUS_CORE_ELAB Single Run MSIE issue: Need support for event for OOPR
1454181 IUS_CORE_ELAB MSIE -nncbind : ncelab crash : vst_offset () - invalid class, class 513,
1471336 IUS_CORE_ELAB MSIE: genhref CPU Usage is not reported in irun.log file
1451783 IUS_CORE_ELAB ncelab TYCMPAT error in MSIE flow with multiple primary partitions
1454221 IUS_CORE_ELAB MSIE OOPR and -nncbind : Support for real port in OOPR
1462194 IUS_CORE_ELAB False port size mismatch warning (DSSSIZ)
1454166 IUS_CORE_ELAB MSIE -nncbind : testcase gives warning SVBNOI but does not give CUVHNF
1452358 IUS_CORE_ELAB ncelab error message sslu_descend - NULL ipp
1453307 IUS_CORE_ELAB MSIE : bind <bind_target_module>: <bind_target_instance_name> <bound_module_name> <bound_module_inst_name> not working
1454167 IUS_CORE_ELAB MSIE -nncbind : ncelab: *E,INCUSC [MSIE] : Module scope bind dot star port instantiation does not work
1454807 IUS_CORE_ELAB Need error for OOPR to unsupported object type/kind
1458444 IUS_CORE_ELAB *E DYNGHE hierarchical reference from primary to incr not allowed
1459031 IUS_CORE_ELAB mccodegen causes Internal Exception and unknown or ambiguous options ( -MSIESINGLEIRUN)
1456762 IUS_CORE_ELAB MSIE: Internal Error when elaborating the design hierarchy - incremental partition
1454183 IUS_CORE_ELAB MSIE : ncelab: *E,DSSUSC (./test.sv,14 35): [MSIE] Unsupported port connection identified.
1459635 IUS_CORE_ELAB During incremental, source files were re-compiled again, even they didn't change since primary build
1459736 IUS_CORE_ELAB ncelab error: code generation failed
1456137 IUS_CORE_ELAB MSIE OOPR : bit support needed for SOC Environment
1458319 IUS_CORE_ELAB ncelab error: sv_seghandler - trapno -1 addr((nil))
1522034 IUS_CORE_ELAB tranif gate turn-on/off delay is shown when data is changed only in the MSIE environment.
1514977 IUS_CORE_ELAB MSIE Simulation difference due to issues in OOPR extern file generation
1519408 IUS_CORE_ELAB two "-iprof" option will cause msie report false error
1520451 IUS_CORE_ELAB INTERR: gq_static_wormhole_offset - incompatible instance
1014100 IUS_CORE_ELAB A source code in primary snapshot is not updated in incremental elaboration
1453584 IUS_CORE_ELAB -primparallelelab -timedetail crash : irun: doit.c:14128: irun_td_mark: Assertion `irun_td_name == ((void *)0_`f failed
1427778 IUS_CORE_ELAB CU scope bind causes CUVHNF error
1495202 IUS_CORE_ELAB INTERNAL EXCEPTION: via_pib_field: No pot or pib assigning AOI to virtual interface array
1486215 IUS_CORE_ELAB Same module/package given on -top and -incrtop with -mkprimsnap should give an error
1497004 IUS_CORE_ELAB MSIE Internal Exception on DENALI VIP ENET Example
1499698 IUS_CORE_ELAB *E,DSSARR *E,DSSUFL: Please add support in MSIE for unsupported port type and array in port expression
1499734 IUS_CORE_ELAB IncElab: Incorrect behavior with tranif1 gate that crosses the snapshot boundary
1494436 IUS_CORE_ELAB 1-irun MSIE : crash on incremental snapshot build
1505625 IUS_CORE_ELAB MSIE: ncelab Internal Exception sv_seghandler - trapno -1 addr(0xffffffffffffffff)
1486218 IUS_CORE_ELAB Please give warning that amkprimsnap -incrtop is deprecated name of -incrbind
1495850 IUS_CORE_ELAB INTERNAL EXCEPTION: vst_libname() - bad class, class 1023
1497851 IUS_CORE_ELAB Ncelab internal exception error while building incremental snapshot
1484859 IUS_CORE_ELAB SINGLE-MSIE: Incorrect DYNGPE error when OOMR goes from one ancillary top to another in same primary
1487845 IUS_CORE_ELAB NC crash during elaboration
1486059 IUS_CORE_ELAB ncelab error INCUSC : support for port of type struct on boundary port
1504805 IUS_CORE_ELAB STIDTP in 1-step irun MSIE flow with -primparamsok
1500618 IUS_CORE_ELAB ncelab *E,DSSUFL for arrays in port list
1490759 IUS_CORE_ELAB INTERR when trying to use MSIE
1490806 IUS_CORE_ELAB MSIE clone creation reaches endless loop
1471679 IUS_CORE_ELAB Incremental snapshot build takes more time even if the number of instances reduced
1507958 IUS_CORE_ELAB with 15.10.002, use tfile to disable tcheck doest work
1460309 IUS_CORE_ELAB ncelab: *E,DSSWLP (./dsswlp.sv,8 11): [MSIE] Too many module port connections.
1479186 IUS_CORE_ELAB vhdl instances not mapped to verilog primaries
1480567 IUS_CORE_ELAB Unexpected DIMERR on 1-step irun
1478356 IUS_CORE_ELAB ncvlog_cg crash with multi primary snapshot MSIE
1474911 IUS_CORE_ELAB Incremental elaboration gets INTERNAL EXCEPTION while running msie pii mode using single irun flow
1469217 IUS_CORE_ELAB MSIE unsupported connection type in 14.21.033 not in 14.21.023
1462262 IUS_CORE_ELAB Why does HREF generation take so long?
1479601 IUS_CORE_ELAB MSIE crash during elaborating primary partition
1469706 IUS_CORE_ELAB irun: *F,MLFNA error with MSIE flow
1475999 IUS_CORE_ELAB Need a release on 14.22 stream for reducing genhref time (irun with ano_ca_prune ) on GLS design
1458914 IUS_CORE_ELAB low CPU utilization during ncelab casued by accessing all source code
1411203 IUS_CORE_ELAB ncelab performance issue
1428182 IUS_CORE_ELAB low CPU utilization during ncelab casued by accessing all source code
1432986 IUS_CORE_ELAB ncelab performance improvement
1484729 IUS_CORE_ELAB Crash on FSL Treeruneer with latest 14.22 release
1484211 IUS_CORE_ELAB Elaboration time increased from 45 minutes to 15hrs
1469901 IUS_CORE_ELAB ncelab performance is slower in new netlist flow when compared to the existing netlist flow.
1460353 IUS_CORE_ELAB Request ability to specify more than 4 cores to -mcmaxcores
1472498 IUS_CORE_ELAB if_write() - closure - unable to locate dep src
1470111 IUS_CORE_ELAB [Mini regression GLS Elab Fail] MSG: if_write() - closure - unable to locate dep src /path_to/a_lib.v
1534749 IUS_CORE_ELAB MSIE : very long incremental elaboration step
1334870 IUS_CORE_ELAB CUVMPW when $clog2 participates in a typedef
1446902 IUS_CORE_ELAB logic type MDA causes ncelab internal cu_propagate_expand width conflict
1451046 IUS_CORE_ELAB code gives unexpected TYCMPAT error for a particular value of the parameter
1457876 IUS_CORE_ELAB INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr(0xf) / cu_propagate_expand - width conflict
1454148 IUS_CORE_ELAB defparam argument caused elaboration Internall exception message cu_double_cmp_classspec
1459062 IUS_CORE_ELAB INTERNAL EXCEPTION: cu_build_glom_ots - VST_POT_LINK is NULL class 513
1515558 IUS_CORE_ELAB ncelab tool failure using UVM 1.2
1358241 IUS_CORE_ELAB SHIP-688 struct param overrides sometimes ignored
1429720 IUS_CORE_ELAB Internal error in GLV elaboration
1418082 IUS_CORE_ELAB $bits in interface is not working correctly
1426680 IUS_CORE_ELAB INTERNAL EXCEPTION: cu_build_glom_ots - VST_POT_LINK is not NULL, class 513
1497027 IUS_CORE_ELAB crash of simulator when loop over a two dimensional associative array indexed by class handle
1486349 IUS_CORE_ELAB Internal exception in elaboration.
1485585 IUS_CORE_ELAB irun fails with "vector ring corrupt" error
1503572 IUS_CORE_ELAB Internal error " rn_create_intoclassref " with virtual interface reference
1404808 IUS_CORE_ELAB ncelab failure on SV 'let' construct
1473695 IUS_CORE_ELAB unexpected ncelab: *E,TYCMPAT
1474302 IUS_CORE_ELAB Ncelab freezing at "Building instance overlay table"
1472054 IUS_CORE_ELAB ncelab internal error with just the production 14.10 releases
1469888 IUS_CORE_ELAB nc elab fails with *F,INTERR: INTERNAL EXCEPTION
1462979 IUS_CORE_ELAB Internal exception error during elaboration
1469259 IUS_CORE_ELAB ncelab tool Internal Exception
1536256 IUS_CORE_ELAB INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr((nil)) with UVM CDNS-1.2
1450323 IUS_CORE_ELAB [NCELAB Internal Exception] request for zero bytes from ha_alloc()
1461899 IUS_CORE_ELAB ncelab: *F,INTERR: INTERNAL EXCEPTION (request for zero bytes from ha_alloc)
1510087 IUS_CORE_ELAB ncelab: *E,CUASMM: Invalid vector width (zero elements) specified for port 'STAT_S_AXI_GEN_RD_SEGMENTS' of
1527850 IUS_CORE_ELAB ncelab internal error: sv_seghandler - trapno -1 addr(0x4bd)
1506078 IUS_CORE_ELAB erroneous *E,TRASMM2 error
1513317 IUS_CORE_PARSE Problem propagating a parameter to a lower level module, $bits is used
1521534 IUS_CORE_PARSE ncelab INTERNAL EXCEPTION MESSAGE: vxt_valloc - unknown
1517874 IUS_CORE_PARSE `Ifdef not being honoured with `protected with multiple files
1524785 IUS_CORE_PARSE ncvlog: *F,NESTPT: illegal nested `protected source.
1522795 IUS_CORE_PARSE ncvlog SIGSEGV error when compiling verilog variant
1508734 IUS_CORE_PARSE ncelab: *F,INTERR : vst_metrics_sampled - vst_TY_tag - default
1418511 IUS_CORE_PARSE ncelab internal exception with message sv_seghandler - trapno
1515936 IUS_CORE_PARSE Comma causes ncvlog INTERNAL EXCEPTION
1500409 IUS_CORE_PARSE NCVLOG failure:: "p2_mpist - no table"
1502843 IUS_CORE_PARSE Freescale Ottawa AIOP_WRKS_FDMA NCVLOG *F, INTERR
1506272 IUS_CORE_PARSE Non-static class methods should not be allowed in constant expressions
1503804 IUS_CORE_PARSE Ncvlog internal error during CASE block compilation under uvm.
1421824 IUS_CORE_PARSE Simvision source browser shows bold line numbers (enable BPs) in wrong lines
1412798 IUS_CORE_PARSE INTERNAL EXCEPTION: ncvlog: p2_mpist - no table
1467660 IUS_CORE_PARSE enhance AMS to reflect high impedance from spice to "Z" on logic side
1487131 IUS_CORE_PARSE ncvlog internal error vst_datatype () - invalid class, class 850
1531677 IUS_CORE_PARSE ncvlog: *F,NESTPT: illegal nested `protected source. when compiling macro model
1526261 IUS_CORE_PARSE PORTNO error
1526265 IUS_CORE_PARSE ncvhdl_p internal error
1531814 IUS_CORE_PARSE elaboration error for port width mismatch
1154341 IUS_CORE_SIM problems at VHDL/ SV boundary
1367120 IUS_CORE_SIM ncsim extremely slow in forcing large unpacked array
1438322 IUS_CORE_SIM Output of AND gate is 'x' when inputs are stable
1439341 IUS_CORE_SIM LPS peformance bottleneck for huge array at corrution
1448585 IUS_CORE_SIM ncsim internal error
1446307 IUS_CORE_SIM Improved error reporting for ssslib errors in releasing objects in VPI
1454688 IUS_CORE_SIM Internal error in ncsim while dumping SAIF file
1460905 IUS_CORE_SIM IUS dumping SAIF without escape character
1508720 IUS_CORE_SIM Internal Exception in $nc_deposit/$nc_release for empty string argument
1509502 IUS_CORE_SIM assign statement value change 0–>x and x–>0 not well taken by tool at the start of simulation
1428814 IUS_CORE_SIM "stream shell stream for power (method)" took 24% hits from one module in customer design
1433605 IUS_CORE_SIM got into an infinite loop if it enables LPS in 14.20.008
1486251 IUS_CORE_SIM Different IES version has different simaultion result when simulate DFT pattern
1497599 IUS_CORE_SIM Need support for X->0/1 transition with dumpsaif
1503896 IUS_CORE_SIM ncprotect Not encrypting all files and segmentation fault
1532824 IUS_CORE_SIM ncsim: *F,INTERR: INTERNAL EXCEPTION sv_seghandler - trapno -1 addr((nil))
1322280 IUS_CORE_SIM Null character on irun command causes uvm to issue fatal NOCOMP message
1356899 IUS_CORE_SIM irun doesn't understand (i.e. ignore) +arg with "/*"
1370018 IUS_CORE_SIM Irun always recompile all files even though nothing is changed
1418538 IUS_CORE_SIM Testcase re-elaboration happens (without modifying any file) with option "-incdir".
1436696 IUS_CORE_SIM ICFUC warning behavior is different between 14.1 and 14.21
1462118 IUS_CORE_SIM irun: *E,CFNOPT error when writing logfile to null device
1377362 IUS_CORE_SIM IDA fails at compilation with cryptic error message
1413807 IUS_CORE_SIM irun keeps re-elaborating the design even if nothing has been changed
1427264 IUS_CORE_SIM Recompile fails to detect changes with -ncerror
1493643 IUS_CORE_SIM cannot open shared object by 14.1s33
1498688 IUS_CORE_SIM use of irun nclibdirname option for specman e and hdl give error
1495510 IUS_CORE_SIM "irun -helpsubject timing" does not show -maxdelay option
1499964 IUS_CORE_SIM Error: dlopen failed: ./INCA_libs/irun.lnx8664.15.10.nc/specman.15.10.005-s/scratch/libsn_precomp.so
1497081 IUS_CORE_SIM specman e + hdl snapshot load error for irun command having nclibdirpath
1502309 IUS_CORE_SIM Irun doesn't recompile C source if -cpost option is used to compile DPI
1498985 IUS_CORE_SIM specman e + hdl snapshot load error for irun command having nclibdirpath
1402052 IUS_CORE_SIM irun fails to recompile after source change for elaboration error
1399574 IUS_CORE_SIM ncelab: *E,CNTSEV: Error 'ICFUC' cannot increase severity promoting all warnings to errors
1415072 IUS_CORE_SIM re-elaboration detected with no file change
1464691 IUS_CORE_SIM irun: *E,CFNOPT error writing the log in a project directory
1507558 IUS_CORE_SIM ncsim: *W,SMNPIE: "ida_probe …."
1477785 IUS_CORE_SIM irun doesn't take nncbind as a hard elab option
1453304 IUS_CORE_SIM MESSAGE: xprepare_license_or_die - maxIndex (-1) less than
1329242 IUS_CORE_SIM VHDL/SV connecting enum ports gives - ncelab: *E,CFMPTC : VHDL port type is not compatible with Verilog.
1335967 IUS_CORE_SIM Support for complete records, nested records and array of records in mixed OOMRs
1455865 IUS_CORE_SIM ncelab: *E,DTYPMSM connecting array of enum ports using types defined by vhdl package import
1449286 IUS_CORE_SIM VHDL to SV Port Binding: Need support for connecting array-of-enum ports
1454515 IUS_CORE_SIM [NGTPMS] VHDL port (DCORE_SV_BIND.NR_STRUCT_I) type is not compatible with Verilog
1514845 IUS_CORE_SIM $nc_mirror to vhdl where generic is referenced in signal declaration causes sv_fpehandler - user generated SIGFPE
1410021 IUS_CORE_SIM LHS of SystemVerilog assignment is not toggling per RHS.
1484640 IUS_CORE_SIM TRSRANGE error on VHDL port in SV testbench
1483470 IUS_CORE_SIM Invalid *E,ASRTST comparing array of integer between VHDL and SV
1472940 IUS_CORE_SIM VHDL record real is not propagated to Verilog struct real
1474742 IUS_CORE_SIM SV OOMR to VHDL Package gives Internal at sim run time: sv_seghandler - trapno -1 addr(0x2c)
1454173 IUS_CORE_SIM MSIE -nncbind : TCL Command "scope -show" results ncsim crash
1440853 IUS_CORE_SIM MSIE got internal error with customer's PLI
1491474 IUS_CORE_SIM design file search and design file list doesn't show files compiled in primary snapshot
1487638 IUS_CORE_SIM simulation run time failure in via_inst_sanity_check
1479196 IUS_CORE_SIM NY SOC 1-irun MSIE testcase simulation time degradation by 4X
1529515 IUS_CORE_SIM Getting error when trying to use '-statement' switch in database command
1416819 IUS_CORE_SIM mcdump on digital signal with AMS sims
1510507 IUS_CORE_SIM Internal Exception error and stuck test when using mcdump with Indago recording
1502899 IUS_CORE_SIM SCABRT: Signal SIGABRT raised outside of simulator
1500793 IUS_CORE_SIM Please improve performance on mixed VHDL & Verilog with UVM SV testbench sims
1342093 IUS_CORE_SIM Simvision does not show UVM hierarchy when a probe command is issued after hitting a breakpoint. in simulation.
1451057 IUS_CORE_SIM Internal Exception due to ivia_pair_sanity_check
1441362 IUS_CORE_SIM Simulation stuck with IDA recording
1456631 IUS_CORE_SIM vst_name invalid class name when ida is dumped
1457746 IUS_CORE_SIM SAIF dumping is taking too long.
1458510 IUS_CORE_SIM SARC IDA Issue: Missing SmartLog Messages even though log recording enabled
1456646 IUS_CORE_SIM ssl_shm_add_scope - not a scope
1517403 IUS_CORE_SIM [NCSIM] internal error: map_xst_class_to_dwScopeType - kind? got:14
1526838 IUS_CORE_SIM Internal exception occurred during simulation
1514399 IUS_CORE_SIM simulation Internal Exception: vst_class
1518007 IUS_CORE_SIM Failure with ncsim tool when recording with IDA
1517993 IUS_CORE_SIM simulation crashed - sslu_shm_sv_update_queue - un-expected transaction type
1291823 IUS_CORE_SIM TLM fifos / mailboxes can't be seen in Simvision waveform window
1289797 IUS_CORE_SIM Unable to probe Mailbox
1508933 IUS_CORE_SIM indago causes an ncsim tool failure
1506948 IUS_CORE_SIM Saved command script doesn't preserve probe_unpacked_limit.
0938785 IUS_CORE_SIM Show SystemVerilog mailbox transactions in simvision
1304387 IUS_CORE_SIM probe command issued after build phase complete or at t=1 doesn't work on uvm hierarchy
1532710 IUS_CORE_SIM INTERR when probing with "-depth all" in INCISIVE151. INCISIV142 works fine.
1407162 IUS_CORE_SIM With -memdetail option the simulation run consumes 2x run time memory
1450592 IUS_CORE_SIM nncbind with -iprof crash simulation
1438453 IUS_CORE_SIM IES out of memory error with mem_iprof on design
1441579 IUS_CORE_SIM ncsim failure wafter simulation finished when trying to write iprof database
1510805 IUS_CORE_SIM Profiler does not show fork join inside a class method like how it is shown inside a module
1500214 IUS_CORE_SIM -rdprofile gives PRFMXSO fatal error
1506440 IUS_CORE_SIM IPROF failure in ncsim *F
1471812 IUS_CORE_SIM iprof to better detail performance slowdown
1455898 IUS_CORE_SIM Internal Exception while probing with -smart
1452274 IUS_CORE_SIM $finish(2) does not execute final blocks in customer simulation
1456685 IUS_CORE_SIM Wait statement is not unblocking after the extrusion is evaluated true
1518509 IUS_CORE_SIM Failure caused by dumpsaif Tcl command used on SV RTL design
1463655 IUS_CORE_SIM Possible memory leak in SV environment
1371499 IUS_CORE_SIM ncvlog internal dt_is_array hit unknown datatype
1437537 IUS_CORE_SIM nscim crash when refering to CB by hierarchical reference
1439041 IUS_CORE_SIM Inconsistent force release semantics for wires and vairables
1409051 IUS_CORE_SIM dynamic array in a task of class problem with fork join_none
1472561 IUS_CORE_SIM Difference in Simulation Behavior with 14.22.016 compared to 14.22.008
1469303 IUS_CORE_SIM Elab mem profile shows one checkpoint at 6.7 hours
1480418 IUS_CORE_SIM Tool failure during simulation caused by uvm optimizations
1478403 IUS_CORE_SIM ncsim : *F, INTERRR: INTERNAL EXCEPTION
1467172 IUS_CORE_SIM IUS simulation Internal Exception in SoC environment
1491547 IUS_CORE_SIM INTERNAL EXCEPTION: sv_fpehandler - SIGFPE not in_rts_xfer (1)
1443242 IUS_CORE_SIM Failing PSL assertion in 14.20.009 was passing in 14.20.003
1203675 IUS_CORE_SIM [Xprop] Reduce the pessimism in case statements
1259978 IUS_CORE_SIM x-prop support for statement with timing delay
1322854 IUS_CORE_SIM XPROP disabled for block with a struct member assignment
1454545 IUS_CORE_SIM Performance degradation when enable xprop
1465914 IUS_CORE_SIM Slow down of x5 when applying xprop
1444812 IUS_CORE_SIM xfile support for hierarchical configuration using module name
1459688 IUS_CORE_SIM Enabling Xprop causes 7x slowdown
1458489 IUS_CORE_SIM xprop build time failure
1450574 IUS_CORE_SIM XPROP not working on MDAs with ternary operator
1522077 IUS_CORE_SIM Elaboration Internal Exception happens with x-prop enabled
1511557 IUS_CORE_SIM Xprop is disabled for all always blocks if there is a generate block
1523539 IUS_CORE_SIM xprop disabled for rtl blocks containing delay inside generate
1524034 IUS_CORE_SIM Always_ff with synchronous reset is wrongly propagating X's
1531596 IUS_CORE_SIM Xprop is wrongly generating 'x' as the output of a function with casez inside
1530627 IUS_CORE_SIM xprop casez fails for 7 bits but works for 6 bits (both show enabled)
1177629 IUS_CORE_SIM Reduce the pessimism in case statements
1217662 IUS_CORE_SIM ncvlog_cg becomes unresponsive
1291768 IUS_CORE_SIM Request support of env variables in xfile
1278874 IUS_CORE_SIM xprop support for non-synthesizable delay statements
1290320 IUS_CORE_SIM Request support of delays in non-blocking assignment for xprop sim
1345434 IUS_CORE_SIM Xprop support for typedef datatypes as L-Value
1359443 IUS_CORE_SIM Support using env variables in xfile and issue a warning if not supported
1362275 IUS_CORE_SIM Xprop CASEZ/CASEX support for selects having x's in some bits positions
1354842 IUS_CORE_SIM INVXPC: task or system task in block when void function call is used in procedural block.
1421118 IUS_CORE_SIM Casez/Casex propagating 'X' with XPROP CAT mode enabled
1435126 IUS_CORE_SIM xfile does not allow in-line comments
1434384 IUS_CORE_SIM INTERNAL EXCEPTION: Unexcepted signal #11, program terminated (null) parsing xfile
1435124 IUS_CORE_SIM Parser error for extra blank space
1435123 IUS_CORE_SIM INTERNAL EXCEPTION parsing xfile
1501855 IUS_CORE_SIM Support xprop for always with FF and latch (see attached testcase)
1501820 IUS_CORE_SIM Have a warning when edge detection is disabled for always block
1508259 IUS_CORE_SIM Simulation with xprop turned off at beginning of sim of snapshot elaborated with xprop is 29x that of snapshot without
1498764 IUS_CORE_SIM always block doesnt work properly when XPROP is enabled
1493333 IUS_CORE_SIM LP Sim - synchronous reset (always block) remains asserted even though clock and reset change
1506454 IUS_CORE_SIM ncvlog_cg gq_taskfunc_prune_enable - incorrect type
1242501 IUS_CORE_SIM Running with xprop shows a 3x performance hit
1320266 IUS_CORE_SIM Xprop: ability to handle RTL assignment with delay
1319777 IUS_CORE_SIM Unexpected Glitch in RTL Simulation in Xprop mode
1395783 IUS_CORE_SIM Need an option to only show the places where x-prop was not applied
1460384 IUS_CORE_SIM message in sufficient to debug problem "Unsupported LHS in assignment"
1469299 IUS_CORE_SIM xprop changes behavior when data signal is used as a clock edge
1464492 IUS_CORE_SIM False NBA and BA message on xp_elab.log
1462077 IUS_CORE_SIM xrop option cause system failure with VHDL design in 15.1
1536076 IUS_CORE_SIM X-prop : The result is different between 14.2/15.1 and 14.1.
1531073 IUS_CORE_SIM xprop generating unexpected X
1504804 IUS_COVERAGE ncsim *F interr with coverage
1484181 IUS_COVERAGE sv_seghandler with multiple include_ccf
1399742 IUS_COVERAGE Using set_code_fine_grained_merging and set_refinement_resilience together
1462224 IUS_COVERAGE Internal error during coverage dumping
1473428 IUS_COVERAGE ucis_Open causes an internal error when invoked with long relative path
1462388 IUS_COVERAGE Expression coverage collecting runs very slow with generated statements
1500278 IUS_COVERAGE internal error rts_cov_nlevel_decomp_arith expr not found in the list
1461206 IUS_COVERAGE expression coverage issue : vector scoring.
1470651 IUS_COVERAGE set_com causing ncelab to take ~2 days to finish
1134760 IUS_COVERAGE Specifying -covdut becomes mandatory when using -lps_verify
1338181 IUS_COVERAGE coverage isn't shown for the RTL when -lps_verify flag is present
1377952 IUS_COVERAGE Conflict between -lps_verify and default coverage collection behavior
1521795 IUS_COVERAGE Coverage Model Creation takes a long time - using cross of more than 2 coverpoints and ignore_bins with
1496372 IUS_COVERAGE Coverage model dumping performance for large cross using with expression
1501976 IUS_COVERAGE Coverage Model Creation takes a long time
1493581 IUS_COVERAGE get_coverage not returning correct covered and total integers when used in UVM hierarchy
1394872 IUS_COVERAGE problem with functional transition coverage
1478547 IUS_COVERAGE Segfault : Error: 'analyze_vplan' command interrupted: failed to parse value for attribute 'buckets_filter'
1467374 IUS_COVERAGE Cross coverage duplicating bin entries when one of the covergroups has ignore bins in it
1464132 IUS_COVERAGE Running into internal gc_tmpmap - width mismtach during code generation with 14.22.008
1442865 IUS_COVERAGE IMC merge issue
1458414 IUS_COVERAGE INTERNAL EXCEPTION: cov_scope_get_modORgenName - unsupported class VST_D_BIND_SCOPE with nncbind
1456820 IUS_COVERAGE ncvlog crash with vst_identifier -bad class, class 581
1511986 IUS_COVERAGE Instance coverage not properly merging into type coverage results
1512365 IUS_COVERAGE NCSIM crash ::sv_seghandler - trapno -1 addr(0x100000a7d)
1489706 IUS_COVERAGE SVBUNSP: Coverage is not yet supported with this implementation
1504321 IUS_COVERAGE INTERNAL EXCEPTION during coverage dump (VST_D_BIND_SCOPE not supported)
1488024 IUS_COVERAGE late insertion of assertions & coverage modules
1463957 IUS_COVERAGE AVSFST 14.22.015 checkout incubation license for MSIE
1482462 IUS_COVERAGE lookup type from covergroup instance to covergroup type is broken
1484233 IUS_COVERAGE merge is failing for block level to chip level instance
1486950 IUS_COVERAGE crash during elaboration with debug build
1470777 IUS_COVERAGE wrong hierarchical names for per instance covergroup
1450357 IUS_COVERAGE Coverage dumping takes too long
1521959 IUS_COVERAGE coverage build performance is 3-4x slower than regular build
1496845 IUS_COVERAGE Very long simulation times when coverage is enabled
1525670 IUS_COVERAGE "xst_decomp_expr, unknown language 0" message while dumping coverage data at the end of simulation
1435501 IUS_COVERAGE toggle coverage support for array of struct
1497738 IUS_COVERAGE INCISIVE 14.10-s021: simulations fail with coverage
1504393 IUS_COVERAGE initreg0 cause 0->1 toggle coverage not collected
1475071 IUS_COVERAGE Overflow bits in assignment to wire confuse set_com in Toggle Coverage reporting
1456365 IUS_CVE *F, INTERR Internal Exception in BCU testcases
1457048 IUS_CVE SIGUSR with *W,SCV082 before that
1310637 IUS_CVE W,SCV082: INTROSPECTION_INVALID_OPERATOR_0ARG - New with 14.1
1401330 IUS_CVE E,SIGUSR 14.2 version: *W,SCV082: INTROSPECTION_INVALID_OPERATOR_0ARG
1464140 IUS_CVE BOSCH: SCV: wrong scv_smart_ptr return type with SC_INCLUDE_FX defined
1334264 IUS_GLS ncelab fatal error for GLS
1517463 IUS_GLS Ncelab unexpected kind error during elaboration and fails to issue any failure information
1520697 IUS_GLS ncelab: *F,INTERR: INTERNAL EXCEPTION when SDF is used
1517839 IUS_GLS result of operator with bose sides having same constant with nagation is wrong
1517916 IUS_GLS GLS, with SDF elab time Internal Exception
1426321 IUS_GLS ncelab INTERNAL EXCEPTION: MESSAGE: gate_add_shadow_driver_info - not SHDWC
1417606 IUS_GLS ncelab: *F,INTERR: INTERNAL EXCEPTION with INCISIVE 14.20-s006 and 14.20-s003
1465185 IUS_GLS ncelab INTERNL EXCEPTION MESSAGE: ring id is -134217728 whereas max ring id is 134217727
1469549 IUS_GLS Simulation result mismatches with probe enabled and probe disable in GLS zero delay mode
1437853 IUS_GLS INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr((nil)) in strap::get s …_if -cs
1435673 IUS_GLS Gate Level Performance suffers slowdown with respect to RTL
1414731 IUS_GLS sv_seghandler - trapno -1 addr((nil)) when $countdrivers is involved in RTL simulation
1397474 IUS_GLS command line option for optimizing supply0 and supply1
1057957 IUS_GLS Support for wildcard in "tcheck -off "
1376308 IUS_GLS pathdelay_sense be a command-line argument for irun
1447046 IUS_GLS large positive hold time is annotated if the hold time in SDF is negative value
1509586 IUS_GLS ncelab Internal Exception with nettmp_replace - equivalent IDs (0) being requested annotating SDF
1516490 IUS_GLS The path delay value is used for RETAIN annotation.
1147733 IUS_GLS * (wildcard) should be applicable to ncsim tcheck tcl command
1432587 IUS_GLS ncelab issues Internal Exception message for acg_verify_dest_tmp when multi SDF files being read
1495305 IUS_GLS Simulation time SDF annotation to VITAL is not supported but can it be ignored?
1483911 IUS_GLS The result of the timing check differs in ntc_level2 and ntc_level3.
1444603 IUS_GLS [Mini regression failure] AVSFST14.22.011 failed with ths ATPG Serial FULLTIMING case
1457836 IUS_GLS ncelab internal error when using -negdelay option
1461253 IUS_GLS ncsim: *F,INTERR: INTERNAL EXCEPTION
1445278 IUS_GLS NCSIM internal error :: sslu_get_sigp - scalar mismatch 2
1533219 IUS_GLS ncsim fails on simport
1514487 IUS_GLS seq_udp_delay not working when tfile used even though outside tfile instance parameters
1469402 IUS_GLS Wrong timing violation is reported
1379045 IUS_GLS Add the to wire through tcl script during simulation run time.
1500991 IUS_GLS ncelab: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Where is the sbo (sbo == NULL) in negdelay_adjust_intc_load()…
1505002 IUS_GLS -negdelay causes ncelab: *F,INTERR: INTERNAL EXCEPTION when it used with 2 or more SDF files and -sdf_simtime
1512283 IUS_GLS Elab tool failure because of uvm_config_db get in module
1511131 IUS_GLS ncelab tool failure using a netlist created by UNL
1403353 IUS_GLS simulation fails with sslu_get_sigp
1485168 IUS_GLS Pulse which has the same width of gate delay dosn't pass the second gate of two casecaded one.
1472224 IUS_GLS INTERNAL ERROR "MESSAGE: gc_orstore - unknown delay mode"
1460642 IUS_GLS ncsim tool failure on LWD shm dumpping, without LWD ncsim in unresponsive
1138788 IUS_LP Powerdown replay issue with a function without inputs
1531736 IUS_LP ILLCNDM/SWFERR messages not helpful in indicating the source of problem
1341458 IUS_LP Add support for map_retention_cell
1335631 IUS_LP Gate-Level sim to support 1801 and instantiated isolation/retention cells
1339746 IUS_LP the tool should support for the PDF a Boolean expression composed of both
Download File Size:9.25 GB